1. Field of the Invention
This invention relates to digital data communication modulator systems, and more specifically, to phase shift keying modulator devices employed in digital data link communication systems.
2. Description of the Prior Art
Digital communication systems typically transmit information by altering the phase angle of a periodic carrier signal waveform upon command by way of a data modulation or phase code command signal. Oftentimes the phase angle alteration is required to be 180.degree., or a phase reversal of one-half of a cycle of the periodic waveform. In a digital communication system, phase angle reversal is sometimes employed in conjunction with carrier signal frequency hopping, which is the rapid electronic sequencing through a plurality of predesignated carrier signal frequencies at the output of the communication system. The communication system employing frequency hopping transmits each carrier signal frequency for a prearranged period of time. The signal frequency hopping technique is typically employed in spread spectrum communication systems, which are less susceptible to errors caused by the imposition of jamming signals.
An electronic frequency synthesizer is normally used to accomplish such carrier signal frequency hopping. During the time it appears at the system output, each one of the predesignated carrier signal frequencies is bi-phase modulated by means of the introduction of a 180.degree. shift in phase of the carrier signal. Such 180.degree. signal phase shifting is generally accomplished by a bi-phase signal modulator which responds to a change in phase code states of a phase code command signal. In this manner, a digital communications system provides several channels of communication. Each one of the communication channels is associated with a different carrier signal frequency, and information of a digital nature is transmitted and received by altering the phase of the carrier signal by bi-phase modulation. Digital communication is thereby made available for many different communication channels using one set of equipment. This method of bi-phase shift keying (BPSK) modulation is a favored digital communication modulation format in the relevant art.
BPSK modulation is employed both in spacecraft, such as a satellite, and in ground-based digital communication systems which comprise data links that transmit information from one station to another. In particular, for spacecraft communications applications, the size, weight, and power consumption of BPSK modulator devices are extremely important parameters. BPSK modulators are also used to secure transmitted information so that such information content cannot be readily detected.
A conventional BPSK modulator in the prior art has heretofore been designed and built in electronic units using a frequency synthesizer, electronic driver, balanced mixer, and amplifier. A modulator unit of this type, which is depicted in FIG. 1A, requires the use of relatively expensive and complex electronic components.
The modulator unit shown in FIG. IA includes digital frequency synthesizer 10 which is a type of electronic frequency synthesizer that provides a repetitive series of digital words of alternating first and second sequences. The first sequence comprises a series of digital words increasing in value to some predesignated maximum value, and the second sequence comprises a series of digital words decreasing in value to some minimum value. The signal developed at the frequency synthesizer output is a series of digital words which characterize a periodic triangular waveform.
With reference to FIG. IA, digital frequency synthesizer 10 is designed in accordance with the teachings of the prior art and comprises binary accumulator 12 which includes binary adder 14 and delay register 16. Binary adder 14 has two sets of inputs, each having N parallel conductors to which digital words are applied. The input conductors denominated A.sub.1 -A.sub.N receive an externally applied frequency selection digital word which corresponds to the desired fundamental frequency of the synthesizer output signal. The input conductors denominated B.sub.1 -B.sub.N receive from the output of register 16 the digital words appearing at the output conductors of binary adder 14; therefore, the frequency selection word applied to input conductors A.sub.1 -A.sub.N is successively added by binary adder 14 to its then-existing contents.
Register 16 comprises N+1 number of D flip flops of which N number receive at their D inputs a serial stream of digital words appearing on N number of parallel output conductors denominated O.sub.1 -O.sub.N of binary adder 14. Register 16 is interposed between output conductors O.sub.1 -O.sub.N and input conductors B.sub.1 -B.sub.N of binary adder 14 so that the digital words appearing at output conductors O.sub.1 -O.sub.N are applied to the B.sub.1 -B.sub.N input conductors at a rate equal to frequency f.sub.C of the clock signal which is applied to the clock inputs of the D flip flops.
For a binary accumulator 14 with N stages, the most significant bit (MSB) corresponds to a phase of 2.pi./2.sup.1 radians, the least significant bit (LSB) corresponds to a phase of 2.pi./2.sup.N radians, and overflow occurs at 2.pi. radians. Since the angular frequency (i.e., the rate of phase change) .omega.=d.theta./dt=.DELTA..theta..sub.step /T, where T=1/f.sub.C, the output signal frequency can be expressed in terms of the input digital word as Mf.sub.C /2.sup.N+1, where M is the decimal equivalent of the frequency selection word applied to input conductors A.sub.1 -A.sub.N. The synthesizer output signal frequency is determined, therefore, by the accumulator size, clock frequency, and input word.
When incremented by its LSB, binary accumulator 12 develops at its output a series of digital words representing a sawtooth waveform. The accumulator output has an extra bit denominated O.sub.N+1 which provides a signal that changes logic state each time the accumulator overflows. This overflow signal is applied to the D input of the N+1 D flip flop in, and is clocked to the output of, register 16 at a rate equal to f.sub.C. The overflow signal which appears at the output of register 16 is applied to an input of each one of N number of exclusive OR gates included in circuit 18. A different output conductor of register 16 is applied to a second input of each one of the exclusive OR gates in circuit 18. When in the logic 1 state, the overflow signal effectively causes the digital words appearing at the output of frequency synthesizer 10 to represent the successive subtraction of the frequency selection word from the accumulator contents. The result is a serial sequence of digital words which characterize a triangular waveform at the output of circuit 18.
Output register 19 transfers the words in the series to the synthesizer output at a rate equal to the clock frequency f.sub.C. Each word in the series which appears at the output of digital frequency synthesizer 10 corresponds to the accumulator contents at a given time. The adjacent digital words in the series appearing at the output of register 16, therefore, generally differ by a constant value equal to the frequency selection word. (The difference value computed from the digital word appearing at the accumulator output after overflow can be an exception to this relationship.)
Since the frequency f.sub.C of the clock signal applied to register 16 and the number N of stages of binary accumulator 2 generally remain constant, the fundamental frequency of the output signal is tuned by changing the value M of the frequency selection digital word applied to input conductors A.sub.1 -A.sub.N of binary adder 14. The fundamental frequency of the output signal depends upon the successive addition in accumulator 12 of an input word having a value M; therefore, an output signal with a higher fundamental frequency is obtained by increasing the value of M.
It is a known property of the digital frequency synthesizer described hereinabove that continuous-phase tuning to different output frequencies is accomplished when the value of M is changed. This property is especially desirable in applications such as, for example, simulating the creation of Doppler frequencies caused by the relative motion between a satellite transmitter and a relay satellite receiver in asynchronous orbits.
The series of digital words appearing at the output of the digital frequency synthesizer 10 is applied to a digital-to-analog (D/A) converter 20 in order to obtain a continuous-wave analog signal having a triangular waveform characteristic. To develop from the output of a digital frequency synthesizer a carrier signal which comprises fewer harmonic frequency components, the signal having a triangular waveform characteristic may be converted into a sinusoidal analog waveform in accordance with either one of two methods.
In the first method, a series of digital words representing a triangular wave is applied to a digital memory device (not shown) having inscribed therein values corresponding to a sinusoidal function. The memory device is positioned between register 19 and D/A converter 20. The output of the memory device is applied to the input of digital-to-analog converter 20 to provide an approximation to a sine wave analog signal. An electronic filtering device 22 positioned at the output of D/A converter 20 further eliminates harmonic frequency components in the analog output signal.
In the second method, a triangular wave in analog form is applied direct from D/A converter 20 to electronic filtering device 22 to eliminate substantially all frequencies but the fundamental frequency component to provide a sine wave at the fundamental frequency.
The sinusoidal analog signal is applied to an input of an electronic balanced mixer 24, the output of which is applied to electronic amplifier 26 to increase the amplitude of the bi-phase modulated signal. The analog signal appears at the output of amplifier 26 as a sinusoidal waveform with a particular amplitude, period, and phase.
An electronic driver 27 supplies a controlled balanced current to balanced mixer 24, which is used as a signal modulator to vary the phase angle of the sinusoidal carrier signal applied to balanced mixer 24 from frequency synthesizer 10. The phase angle characteristic of the carrier signal is governed by an input signal to electronic driver 27, which is referred to as the phase code command signal. The phase code command signal has first and second voltages which correspond to different phase code states, the first state producing at the output of the BPSK modulator device a carrier signal which differs in phase angle by 180.degree. from that produced by the second state. A change in the state of the phase code command input signal will command a phase angle reversal by 180.degree. of the carrier signal appearing at the output of the BPSK modulation device.